In Table 1, slit and stair pitch are not reduced at the more advanced nodes. Basic dimensional information about the modeled structures are summarized in Table 1. Figure 1 displays a top view of 3D NAND slit and channel holes at the 32P, 64P and 96P nodes, while Figure 2 presents a cross-sectional view of a 3D NAND staircase at these same nodes. To explore this issue further, 32P, 64P and 96P TCAT 3D NAND devices were modeled using reverse engineering reports from TechInsight. Enhancing device density without sacrificing the allowed process window is a key issue in 3D NAND process development.
NAND X CASE WINDOWS
These narrower process windows are needed so that the downstream stair contact will precisely land on the staircase center without shorting the word line at the stair sidewall. Also, shrinking the stair CD and pitch will require a more uniform stair angle along with a much smaller CD variation in the stair etch process. With a smaller channel hole pitch and CD, the allowed process window for other processes (such as the channel hole to channel hole bridge during the etch process, or the channel hole to substrate open in both the etch and deposition processes) will become narrower. For example, if the slit pitch is reduced, the channel hole pitch must also be decreased at the same time. Unfortunately, these changes can introduce many challenges in lithography and downstream etch and gap filling processes. Traditionally, memory cell and staircase area could be reduced by decreasing the CD and pitch of the slit and stair structures. In 3D NAND, slit pitch in the bitline direction, and stair pitch in the cross bitline direction, are two of the most important factors in determining memory cell and staircase area. The Effect of Patterning Schemes on the Process Window
Variations in patterning schemes, and the resulting virtual structures, were modeled using the SEMulator3D ® semiconductor platform. The schemes and data used in this study are based upon (or inferred from) tear down reports published by TechInsights ®. We will compare these schemes to understand their impact on effective transistor density. In this discussion, we will analyze various patterning schemes for staircase and slit structures at different TCAT (Terabit Cell Array Transistor) 3D NAND nodes. At the same time, patterning scheme optimization can also enhance 3D NAND effective device density. Device density can be linearly increased by increasing stack layer counts in a 3D NAND device. In NAND Flash technologies, this has led to the market dominance of 3D structures instead of 2D planar devices. Driven by Moore’s law, memory and logic semiconductor manufacturers pursue higher transistor density to improve product cost and performance.
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